Waferpedia

Agilent

Medalist i 5000 ICT

The Agilent Medalist i 5000 ICT is an un-multiplexed in-circuit tester with a tester-per-pin architecture providing a 1:1 channel-to-node configuration. The Agilent Medalist i 5000 ICT uses a N1141 A test head, and the system is expandable toward a 5,184-node platform maximum.[1]

Medalist i 5000 ICT — Inventory photo
Fig. 01Medalist i 5000 ICTInventory photo[1]

Power

50 Hz (configured for European mains)[1]

Performance

throughput multiplier capable[1]

What it is

The Agilent Medalist i 5000 is an in-circuit tester produced by Agilent Technologies. The system uses a tester-per-pin architecture with one-to-one channel-to-node mapping and operates in an un-multiplexed configuration.[1]

How it works

General reference — not yet source-verified

An ICT applies analog stimulus and measures response through a dedicated set of test pins that contact specific nodes on the printed circuit board. The system can test passive components, diodes, transistors, and integrated circuits for correct placement and value, and can detect manufacturing defects such as solder bridges or missing parts.

Where it fits in the process flow

The Medalist i 5000 is configured as a standalone system without an automated board handler, requiring manual board loading and unloading for each test cycle.[1]

What do the numbers mean?

Power & electrical3

Frequency
50 Hz (configured for European mains)[1]
Accurate?
Power Supplies
8 programmable channels: 2 x Agilent 6624, four channels in each module[1]
Accurate?
Mains Frequency
50 Hz (configured for European mains)[1]
Accurate?

Wafer handling2

No board handler
standalone system, manual board load[1]
Accurate?
No board handler: standalone system, manual board load[1]
Accurate?

Performance2

2 x Ctl_Xtp control cards
throughput multiplier capable[1]
Accurate?
Control Cards
2 x Ctl_Xtp control cards: throughput multiplier capable[1]
Accurate?

Configuration & options9

Test Head
N 1141 A[1]
Accurate?
Config
ATO 46121[1]
Accurate?
Test Head Assembly
N1145 A[1]
Accurate?
64 MB RAM per module
probe location and debug of Module 3[1]
Accurate?
8 programmable channels
2 x Agilent 6624, four channels in each Modul 3 & 3[1]
Accurate?
Architecture
Un-multiplexed, tester per pin, 1:1 channel to node[1]
Accurate?
Board Configuration
18 x Unmex_H 144 Channel hybrid pin cards: 2,592 un-multiplexed nodes[1]
Accurate?
Analogue Stimulus/Response
2 x ASRU_C analogue stimulus/response units, one per module[1]
Accurate?
Memory
64 MB RAM per module[1]
Accurate?

Observed configurations

How individual machines were equipped when they appeared on the secondary market — as listed, per unit. These describe one specific machine, not the model in general.

Unit as listed[1]

  • Tester per pin architecture
  • 1:1 Channel to node
  • Test Head: N 1141 A
  • Config: ATO 46121
  • Test Head Assembly: N1145 A
  • 2 modules populated (Module 2 & 3)
  • two module slots free, expandable toward the 5,184-node platform maximum
  • 18 x Unmex_H 144 Channel hybrid pin cards: 2,592 un-multiplexed nodes
  • 2 x ASRU_C analogue stimulus/response units, one per module
  • 2 x Ctl_Xtp control cards: throughput multiplier capable
  • 64 MB RAM per module: probe location and debug of Module 3
  • 8 programmable channels: 2 x Agilent 6624, four channels in each Modul 3 & 3
  • 50 Hz (configured for European mains)
  • No board handler: standalone system, manual board load
  • Controller PC, monitor arm, keyboard and E-stop included
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What does it need to run?

Site utility requirements, footprint, and infrastructure needed to install and operate this tool. Sourced from public records.

  • Frequency50 Hz (configured for European mains)[1]
  • Power Supplies8 programmable channels: 2 x Agilent 6624, four channels in each module[1]
  • Mains Frequency50 Hz (configured for European mains)[1]

Where are the manuals?

Generated from public-source data on file. Enter your email to access — nothing is published; details are routed privately.

Not publicly documented

Field notes

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Frequently asked questions

What is the tester-per-pin architecture of the Medalist i 5000?

The Medalist i 5000 uses a tester-per-pin architecture with one-to-one channel-to-node mapping and operates in an un-multiplexed configuration.[1]

What is the maximum expandable node count?

The system is expandable to a maximum platform size of 5,184 nodes.[1]

Is the system automated or manual?

The system is standalone with no board handler, requiring manual board loading and unloading.[1]

Not publicly documented

The following facts about the Medalist i 5000 ICT are absent from this record as of this revision. First-hand knowledge or a citation closes a gap; every submission is reviewed before publication.

  • No publicly documented production dates or lifecycle milestones (introduction, end of production, EOL) for the Medalist i 5000 ICT are on record.

    Answerable by: OEM historical records or a trade-press announcement

  • No publicly documented variants, configuration options, or revision breakpoints of the Medalist i 5000 ICT are on record.

    Answerable by: an OEM product catalog or an engineer who ordered or specified the tool

  • The control-system platform and OS era of the Medalist i 5000 ICT are not on record.

    Answerable by: an engineer who operated it or OEM installation records

  • No publicly documented failure modes or field errata for the Medalist i 5000 ICT are on record.

    Answerable by: a field service engineer, process engineer, or maintenance technician

  • The process node or technology generation of the Medalist i 5000 ICT is not on record.

    Answerable by: an OEM datasheet or a fab qualification report

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Sources & citations

Sources (1)Every fact above is drawn from these public sources
  1. [1]Inventory photo
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Last updated Sep 22, 2026.

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